Increasingly complex integrated circuits are being used in applications where the availability of energy is very limited. Such is the case with mobile phones, handheld computers, and other battery-powered electronic appliances. It is important to minimize their consumption by all possible means in order to have sufficient operating autonomy. Now, the integrated circuits consume all the more power when they include a larger number of transistors, and integrated circuits are now being made which include hundreds of millions, even billions of transistors. Volatile memories of SRAM type are in particular used in these appliances, and their capacity can run to millions or billions of memory points, each memory point having, for example, six transistors.
The SRAM solid-state memories need to be supplied with energy even when not being used, to be able to retain their content between uses. If the power supply is cut, the stored information disappears. Since the periods of non-use can sometimes be much longer than the periods of use, attention has to be paid most specifically to minimizing the consumption during the periods of non-use.
Generally, it is common practice to reduce the power supply voltage for the integrated circuits, and notably for the SRAM memories in a standby mode between uses; the normal voltage is then restored, allowing for active operation of the memory in read or write mode when the appliance is to be used again. However, it is still necessary to retain a sufficient power supply voltage in standby mode to guarantee that the information stored in memory is maintained. The limit of this method therefore lies in the choice of a standby voltage that is well suited, both low enough to limit the consumption and sufficient to guarantee that the stored information is maintained.
It has also been proposed to modify the rear face bias voltages of the integrated circuit substrate according to the more or less active use of the appliance: normal mode, standby mode, or even accelerated operating mode.
The patent publication US-2003-080802 moreover describes a circuit for adjusting well bias in normal operation, intended first of all to optimize the speed, and secondarily the current leakages at rest, which can deteriorate if the well bias voltage is ill-matched. This document uses an inverter as detector, this inverter having its output looped back to its input, and this inverter receives specific bias voltages enabling it to operate as detector. The circuit described in this publication does not allow for adaptation of the bias voltages when switching to a very low power supply voltage in standby mode; it works for a standard power supply voltage.